module counter (
    input            clk,    //时钟信号
    input            key,    //按钮输入信号
    input            rst_n,  //复位信号
    output reg [6:0] q       //计数输出信号
);

  reg [23:0] counter;  //内部计数器，用于消除抖动

  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) //复位
        begin
      q       <= 0;
      counter <= 0;
    end
    else if (key) //按下按钮
        begin
      if (counter == 0) q <= q + 1;
      counter <= counter + 1;
    end else  //松开按钮
      counter <= 0;
  end

endmodule
